The present invention relates to a divider circuit.
Signal processing frequently requires output clock signals which are derived from high frequency signals, for example input clock signals, and whose frequency is divided in comparison with the input clock and which have a prescribed phase relationship among one another. What are known as IQ signals, which are required in reception circuits for mobile radio applications, for example, have two real signal components which are 90° out of phase with one another, the I component (Inphase) preceding the Q component (Quadrature) by 90° for positive frequencies and following it by 90° for negative frequencies.
Corresponding frequency divider circuits usually use flip-flops, where a signal is fed back from a data output to a data input, which, in the case of D-type flip-flops, for example, changes the output state upon every positive clock edge. At particularly high input clock frequencies, e.g. in the Gigahertz range, the DQ delay time, that is to say the delay between the application of an input signal level D and the presence of the corresponding signal level at an output Q of the respective flip-flop used, has a disadvantageous effect on the operation of the divider circuit. In this context, the maximum possible input frequency is limited at the top by the DQ delay time of the flip-flops used and any logic circuits which are required.
The delay time of flip-flops designed using conventional CMOS circuitry may be longer than the length of half an input clock cycle. In the past, high input frequencies have therefore prompted a change to embodiments using CML (Current Mode Logic), which has higher associated power losses as a result of constantly flowing currents, however. Particularly mobile radio applications require circuits with very low power consumption and hence very little power loss, however. The majority of complex circuit arrangements in the mobile radio sector are therefore designed using static CMOS technology. If CML circuit parts are then used for fast divider circuits, it is additionally necessary to perform level conversion for CMOS signals. This is associated with additional circuit complexity and further power loss.
To increase the speed of flip-flops designed using CMOS technology, the article “Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements” B. Nikolic et al. in IEEE Journal of solid-state circuits, volume 35, No. 6, June 2000, for example, proposed sense-amplifier-based flip-flops (SAFFs). The article describes an SAFF comprising a differential sense amplifier as master latch and an RS-type flip-flop as slave latch, the sense amplifier stage producing a change from logic High to logic Low level at one of its outputs upon every rising clock edge. The corresponding SAFF is particularly suitable for use in pipeline stages in microprocessors at clock rates of up to 1 GHz.
In the case of frequency divider circuits in receiver or transmitter circuits, for example for mobile radio, ADSL, serial ATA or other wired transmissions, even higher frequencies of a few Gigahertz need to be processed, however. In addition, a duty cycle of 0.5 needs to be provided, as far as possible, for the output clock signal produced at a divided frequency. In this case, it is also beneficial to output a plurality of signals with a prescribed phase shift among one another. By way of example, these may be used as sample control signals in sample/hold circuits or analog-digital converters. Other use options are IQ transmission and reception circuits, which require orthogonal signals.
Embodiments using conventional CMOS logic are also possible, since in that case particularly no static current sources are required, in contrast to Current Mode Logic implementations.